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Eight Benefits of Using an FPGA with an On-chip High-Speed Network (WP020)

 

Published September 2020
Eight_Benefits_of_Using_an_FPGA_with_an_On-chip_High-Speed_Network_WP020

Since the initial introduction of FPGAs decades ago, each new architecture has continued to employ a bit-wise routing structure. While this approach has been successful, the rise of high-speed communication standards has required ever increasing on-chip bus widths to be able to support these new data rates. A consequence of this limitation is that designers often spend much of their development time trying to achieve timing closure, sacrificing performance in order to place and route their design.